Portrait of Ismail Emir Yuksel

Ismail Emir Yuksel

I am a Ph.D. student in the SAFARI Research Group at ETH Zürich, advised by Prof. Onur Mutlu. My research spans computer architecture, processing-in-memory, and hardware security. I focus on understanding, enhancing, and exploiting the computational capabilities and robustness of modern DRAM chips through large-scale experimental characterization.

In particular, I demonstrate that commodity DRAM chips, without any hardware modification, can perform bulk bitwise logic operations, reliability enhancements, and security primitives, while also uncovering and mitigating DRAM read disturbance phenomena such as RowHammer, RowPress, and ColumnDisturb. Prior to ETH Zürich, I received my M.S. and B.S. degrees from TOBB University of Economics and Technology under the supervision of Prof. Oğuz Ergin.

row 0x000 · AUTO SWEEP · activations 0 · bitflips 0

News

Recent updates on papers, talks, workshops, and awards (2026–present).

Research

I experimentally characterize real off-the-shelf DRAM chips using custom FPGA-based infrastructures (DRAM Bender, SoftMC). Each theme below includes a simplified interactive simulation.

01 · Making unmodified DRAM compute

Activating three DRAM rows simultaneously connects all three cells in each column to the same vertical wire (bitline) so they share charge. The sense amplifier resolves the majority value, computing MAJ(A, B, C), A AND B, or A OR B across thousands of columns in parallel.

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02 · Finding how DRAM leaks and breaks

Repeatedly opening or keeping open an aggressor row disturbs unaccessed cells in two ways: RowHammer / RowPress corrupts cells in physically adjacent rows, while ColumnDisturb (MICRO ’25) propagates disturbance along the shared vertical bitlines (columns), inducing bitflips in far rows across the subarray and neighboring subarrays.

Press and hold on any row to hammer it
0aggressor row activations
0adjacent-row bitflips (RowHammer)
0far-row bitflips along columns (ColumnDisturb)
0mitigation refreshes

Hold on any row to hammer it: nearby rows flip via RowHammer/RowPress, while cells sharing the same columns in far rows flip via ColumnDisturb.

03 · In-DRAM security primitives (TRNG & PUF)

Simultaneously activating four rows holding complementary bits (1, 1, 0, 0) drives each column to the metastable midpoint (½VDD). Sense amplifiers either resolve randomly from thermal noise (SiMRA-TRNG) or latch to a repeatable chip-specific bias (SiMRA-PUF).

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Output Bitstream (64-bit):

Publications Google Scholar ↗

37 peer-reviewed papers and preprints (8 as first author, 29 as co-author). Hover any point on the timeline to inspect a paper or click it to jump to its entry below. Also indexed on DBLP.

Publications timeline by topic (2020–2026)
First author Co-author Award

All papers

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Topic

Organized workshops & tutorials

Lead organizer of the Workshop on Memory-Centric Computing Systems (MCCSys) and co-organizer of the Ramulator & DRAM Bender tutorials at top computer architecture and systems conferences.

Invited talks, tutorials & conference presentations

Invited university lectures, workshop tutorials, and conference paper presentations. Click any video snapshot to watch inline.

Academic service & peer review

Reviewer and subreviewer for computer architecture, systems, and hardware reliability venues.

JournalsReviewer
Journal Reviewer
IEEE TETC IEEE CAL
ConferencesSubreviewer
Conference Subreviewer
ISCA MICRO HPCA ASPLOS DSN ICS
JournalsSubreviewer
Journal Subreviewer
IEEE Micro Top Picks IEEE TCAD ACM TECS Microelectronics Reliability